In-article:

Intel: a new design to go below 2 nm


Nerces

Hardware and Gaming Specialist

January 25, 2022 at 09:37

6

wafer

The American founder is filing new patents likely to help him in his quest for processors
ever denser.

While he is probably not the only person responsible for the revival that Intel seems to have experienced since his arrival, Pat Gelsinger – the new CEO of the American company – has clearly given impetus to a new dynamic of which we have a new example today. today.

Germanium stack and film

Just recently, a new patent filed by Intel has emerged online. This is a new design of transistors intended to keep Moore’s Law alive a little longer by conceptualizing ” stacked forksheed transistors which could roughly be translated as “stacked fork transistor”.

The objective is to lead to a three-dimensional design – arranged vertically – of the CMOS architecture. Of course, this should make it possible to considerably increase the number of transistors integrated in the same space compared to the techniques currently in use at Intel, such as the design tri gate which has been going on for years.

In 2019, Intel already presented its first work in this area, but today the thing is a little more precise. The founder explains that the new design makes use of transistors ” nanoribbon”. Their particularity is to be associated with a very thin germanium film which acts as a dielectric separator.

Greatly increase circuit density

This should make it possible to substantially bring the PMOS and NMOS transistors closer together without their operation being disturbed by this proximity. The density of the integrated circuits could thus be increased, but Intel is careful not to mention an improvement on the PPA side (Power-Performance-Area). Undoubtedly the works are still too little advanced.

As explained Tom’s Hardware, Intel is not the first to present work on the subject and a research group based in Belgium has exploited a similar process on a 2 nm engraving node with, as a result, an improvement in the energy efficiency of around 24% compared to traditional designs. The surface used was reduced by 20% and the speed of the circuit could be increased by 10%.

Remember that the filing of a patent is far from always leading to a real product. It is above all a question of protecting research without promises for the future. Since we are talking about the future, TSMC is not sitting idly by either and its 3nm node should achieve 10-15% more performance compared to 5nm with a 30% reduction in consumption.

On the same subject :
Intel Insists: Don’t Overclock Non-K Alder Lakes, Even If It Works

Source: Tom’s Hardware



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