The new generation of processors AMD is scheduled for the middle of next year. It remains to be seen which range(s) will be launched.
Last May, AMD confirmed that it was working on a hybrid architecture for its future Ryzen. Two weeks ago, the first clues related to Strix Point and Strix Halo reached us. Another source confirms all this.
Zen 5 hearts and Zen 5c hearts
The principle of hybrid architecture is nothing really new. It is a question of making CPU cores of different kinds work together with, in the line of sight, the desire to take advantage of the best of each.
So, on your smartphone, you may have noticed the association of Cortex cores of two or even three different types. ARM was indeed one of the pioneers of the architecture, but perhaps you only really heard about it with the launch two years ago of Intel’s Alder Lake line and its performance cores/cores effective.
Officially, AMD has only spoken of its interest in this type of architecture, mentioning the possibility of integrating such a technique with the Ryzen 8000, the next generation of processors from the firm.
4nm burning and shared cache
Today, a second source confirms that this integration could be done with the Strix Point and Strix Halo ranges, two of the Ryzen 8000 series that AMD already has in mind.
Relayed by VideoCardzthis is the website Performancedatabases who claims to have obtained the first captures of Strix Point processors in action. These captures don’t share a lot of detail, but offer a quick overview of features. CPU-Z is not the most talkative, limiting itself to listing processor instruction sets.
HWiNFO is more helpful and first confirms the etching process used (4 nm) as well as the TDP (45 Watts). More importantly, it is clearly stated that the CPU takes advantage of 4 Zen 5 cores and 8 Zen 5c cores. According to the latest news, the former are the most powerful, but contrary to what Intel does, even the less beefy ones have hyper-threading.
Note however that the Zen 5 cores seem to have 1 MB of L2 cache each, while on the Zen 5c cores, the L2 cache would be shared, at the rate of 1 MB per group of 4 cores. Note that this information remains to be taken with hindsight. For example, HWiNFO mentions a clearly incorrect frequency of 8.8 GHz and could therefore be wrong elsewhere.
One thing is in any case certain, AMD is more than ever at work on the Strix Point APUs. The reviewed versions of CPU-Z and HWiNFO are engineering samples that are the second to last step before going into production.
Source : VideoCardz
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