Intel, Samsung, TSMC: this is the top three when it comes to engraving semiconductors. But in what order exactly?
At Samsung, we seem to take seriously the fact that size doesn’t matter and control is everything.
Samsung ambushed in the Intel/TSMC duel
Late since its setbacks on the 10 nm engraving process, Intel is also very ambitious. At the end of June, Pat Gelsinger, the CEO of the group, showed confidence in the return to business of the company.
He even had a very clear double objective in his sights: to become number two again in the very closed universe of high-performance engraving (ahead of Samsung, but behind TSMC) and to overtake the Taiwanese company in order to regain technical leadership at the horizon 2025.
In these “predictions”, Intel certainly takes into account the work of TSMC, but seems to pay little heed to Samsung’s progress.
Better performance on 3 nm
The South Korean company is however far from twiddling its thumbs, and it is also advancing both on the validation of the engraving process in 2 nm, but also on the optimization of the process in 3 nm.
It is moreover on this second point that news reached us thanks to our colleagues from TechPowerUp. News in two parts with, first, details concerning the efficiency of 4 nm engraving at TSMC and at Samsung. The first actually has a slight advantage with 80% efficiency, when Samsung has to settle for 75%.
4nm is the latest process to exploit FinFET technology. With 3 nm, we are talking about initiating the cycle of GAAFET, a technology on which Samsung has great hopes. It would also in this area yields slightly higher than those of TSMC: 60%, against 55%. Higher throughput logically leads to more operational chips on each wafer and, in doing so, lowers costs.
Of course, this information is advanced by Samsung, and we would have to see if, internally, we say the same thing at Intel or TSMC.
Source : TechPowerUp
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