AMD’s Zen 5 architecture promises, but these are on the processors Strix Point and Strix Point Halo that we will have our eye on for their amazing Zen 5/RDNA 3.5 cocktail.
Over the whole of 2023 and the beginning of 2024, we experienced a rather quiet period on the microprocessor side. Things should change very quickly.
Between the second half of this year and the first half of 2025, we should indeed see several ranges emerge, from AMD as well as from Intel, with architectures as promising as the Strix Point of the first and the Arrow Lake of the second.
Strix Point, then Strix Point Halo
For AMD, from the end of the year, Strix Point will be an opportunity to highlight the Zen 5 cores, which will also be integrated into the Granite Ridge desktop processors, although with one notable difference.
Granite Ridge should only integrate a minimalist graphics solution with two RDNA 2 calculation units, while Strix Point presents itself as a much more muscular APU with 16 RDNA 3.5 calculation units through what we call 8 WGP (or WorkGroup Processors) to support the 12 Zen 5 cores made up of 4 Zen 5 and 8 Zen 5c.
The documents cited by HKEPC and relayed by VideoCardz confirm this various information and also specify that the Strix Point APUs will be able to count on a second level cache of 12 MB, when the L3 cache will be 24 MB. Strix Point will be equipped with AI XDNA 2 acceleration and a TDP between 45 and 65 watts.
Note that the display will be dedicated to DisplayPort 2.1 technology, however with UHBR10 (maximum speed of 10 Gbps) as a limit. Finally, there is talk of AMD offering the management of 16 PCI Express Gen 4 lines with its processors. No, no PCIe Gen 5.
No less than 40 RDNA 3.5 calculation units!
Strix Point is due to launch at the end of the year, without AMD having given a more precise launch window for the moment. This range will, however, be quickly followed by Strix Point Halo, which should drive the point home.
While Strix Point is made up of well-endowed APUs on the iGPU side, Strix Point Halo goes much further. The 12 Zen 5 cores are swapped here for 16 Zen 5 cores, however with the same cache ratio. In total, we will therefore have 16 MB of L2 cache and 32 MB of L3 cache on this range. However, it is on the graphics side that the progress seems to be the most important.
Indeed, the documents from our colleagues here mention a whopping 20 WGP for what seems to be a total of 40 RDNA 3.5 calculation units. We can’t wait to see such a monster at work, especially since the beast is supported by 32 MB of so-called “MALL” cache, the operation of which seems quite similar to that of the current Infinity Cache.
Of course, XDNA 2 is also in order, but while AMD is talking about 50 TOPS (trillion operations per second) on Strix Point, it is talking about 60 TOPS on Strix Point Halo. Another progress, the LPDDR5X-8000 memory is managed by Strix Point Halo, when Strix Point has to make do with LPDDR5X-7500, but of course, the TDP is increasing.
The envelope of Strix Point Halo is thus between 70 and 130 watts. This last point will logically reduce the field of action of Strix Point Halo, which should however find its place where graphics power is very important, but where available space prevents the integration of a dedicated graphics card.
Sources: HKEPC, VideoCardz
Having fallen into video games at a time when it took a great imagination to see here a football match, there a tank fight in these few bars represented on the screen, I have followed all the developments for forty years. Loyal to the PC, but a fan of all genres, I only have trouble with JRPGs. Otherwise, from the driest turn-based strategy to the most spectacular FPS, including sports simulations or musical games, I can do it all... with a preference for management and games combining several styles. My video game pantheon would consist of three series: Elite, Civilization and Max Payne.
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