NASA has chosen SiFive, an American start-up specializing in the design of RISC-V processors, to provide the “processor core” of the space agency’s next HPSC (High-Performance Spaceflight Computing) processor. The agency announced last June that its HPSC project aims to develop a new computing technology for spaceflight, the computing capacity of which will be “at least 100 times” greater than that of current computers, developed nearly 100 years ago. 30 years.
These new CPUs will not only have to be radiation resistant, but also run on minimal power and shut down when not needed, while being able to land spacecraft on Mars and assist astronauts in space. Engineers at NASA’s Jet Propulsion Laboratory (JPL) are leading the development of the HPSC to provide multi-core chips and its operating software. The HPSC must process data 100 times faster than existing “space-qualified” computers due to power constraints.
That’s why the space agency eventually turned to RISC-V chip designer SiFive to help replace its aging spaceflight computers. According to SiFive, NASA’s HPSC will use an eight-core SiFive X280 “Intelligence” RISC-V vector core, along with four other SiFive RISC-V cores.
The chip designer claims that the X280 has demonstrated a 100x speed increase over that required for NASA’s HSPC, and is suitable for applications requiring high throughput, single-wire performance, and constraints of consumption. “Our SiFive RISC-V IP enables NASA to benefit from the support, flexibility and long-term viability of the growing global RISC-V ecosystem,” said Jack Kang, Business Development Manager at SiFive. .
A victory for the RISC-V standard
NASA’s choice of SiFive is a small but important victory for the RISC-V (pronounced “risk-five”) standard. The latter was invented by professors David Patterson and Krste Asanović, of the University of California, Berkeley, 12 years ago. Developers are free to modify the instruction set architecture (ISA) of a RISC-V chip, which defines how the hardware of the chip operates. This differentiates it from Intel’s closed x86 ISAs, which dominate PCs and servers, and Arm instructions licensed by Arm Ltd to most smartphone manufacturers, which have proven popular for M1 chips. from Apple, for example.
Intel also sees opportunities in RISC-V chips after it launched Intel Foundry Services (IFS) last year and returned to making chips for others. In February, Intel joined RISC-V as a Core Member and, along with IFS, announced a $1 billion fund to strengthen tools for x86, Arm, and RISC-V ISAs. Intel is also making high-performance RISC-V cores from start-up Ventana Microcro available to IFS.
In August, NASA’s JPL announced that it had selected US industrial embedded control systems developer Microchip Technology to develop its HPSC processor. Microchip Technology was responsible for the architecture, design and delivery of the HPSC processor over three years under a $50 million contract. NASA’s announcement doesn’t mention RISC-V, but Microchip announced the industry’s first RISC-V-based field programmable gate array (FPGA) SoC in June.
According to Microchip, its design will allow NASA to benefit from “full Ethernet networking, advanced artificial intelligence and machine learning processing, and connectivity support.”
Source: ZDNet.com